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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
FEATURES
* Four SSTL_2 differential clock output pairs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.80ps (typical) * SSTL operating voltage supply ranges: VDD = 3.0V to 3.6V, VDDO = 3.0V to 3.6V VDD = 2.3V to 3.6V, VDDO = 2.3V to 2.7V VDD = 2.3V to 3.6V, VDDO = 1.7V to 1.9V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS848004I is a 4 output SSTL_2 Synthesizer optimized to generate Fibre HiPerClockSTM Channel reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz. The ICS848004I uses ICS' 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS848004I is packaged in a small 24-pin TSSOP package.
ICS
FREQUENCY SELECT FUNCTION TABLE
Inputs Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 23.4375 F_SEL1 F_SEL0 0 0 1 1 0 0 0 1 0 1 1 0 M Divider Value 24 24 24 24 24 24 N Divider Value 3 4 6 12 4 3 M/N Divider Value 8 6 4 2 6 8 Output Frequency (MHz) 212.5 159.375 106.25 53.125 156.25 187.5
PIN ASSIGNMENT
nQ1 Q1 VDDo Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD F_SEL1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VDDO Q3 nQ3 GND nc nXTAL_SEL TEST_CLK GND XTAL_IN XTAL_OUT
ICS848004I
BLOCK DIAGRAM
F_SEL[1:0] Pulldown nPLL_SEL
Pulldown
2
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View Q0
1 F_SEL[1:0] 0 0 /3 0 1 /4 10 11 0
Q2 nQ2 nQ0 Q1 nQ1
TEST_CLK Pulldown
26.5625MHz
1
XTAL_IN
OSC
XTAL_OUT nXTAL_SEL
Pulldown
0
Phase Detector
VCO 637.5MHz
(w/26.5625MHz Reference)
/6 /12
M = 24 (fixed)
Q3 nQ3
MR
Pulldown
The Advance Information presented herein represents a product currently in design or being considered for design. The noted characteristics are design targets. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 848004AGI www.icst.com/products/hiperclocks.html REV. A JUNE 17, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
Type Description Differential output pair. SSTL_2 interface levels. Output supply pins. Differential output pair. SSTL_2 interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Power supply ground. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. SSTL_2 interface levels. Differential output pair. SSTL_2 interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 22 4, 5 6 Name nQ1, Q1 VDDO Q0, nQ0 MR Output Power Ouput Input
7 8, 18 9 10, 12 11 13, 14 15, 19 16 17 20, 21 23, 24
nPLL_SEL nc VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN GND TEST_CLK nXTAL_SEL nQ3, Q3 Q2, nQ2
Input Unused Power Input Power Input Power Input Input Output Output
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 58.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V10%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.0 3.0 3.0 Typical 3.3 3.3 3.3 TBD TBD TBD Maximum 3.6 3.6 3.6 Units V V V mA mA mA
TA = -40C TO 85C
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V10% OR 2.5V10%, VDDO = 2.5V10%,
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.3 2.3 2.3 Typical 3.0 3.0 2.5 TBD TBD TBD Maximum 3.6 3.6 2.7 Units V V V mA mA mA
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V10% OR 2.5V10%, VDDO = 1.8V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.3 2.3 1.7 Typical 3.0 3.0 1.8 TBD TBD TBD Maximum 3.6 3.6 1.9 Units V V V mA mA mA
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V Minimum Typical 2 1.7 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V A
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current TEST_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL, TEST_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL,
VDD = VIN = 3.6 or 2.7V VDD = 3.6V or 2.7V, VIN = 0V
IIL
-150
A
TABLE 3E. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V10%, TA = -40C TO 85C
Symbol Parameter VOD VPP VCMR VOH Output Differential Voltage Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1 Output High Voltage; NOTE 2 Test Conditions Minimum 0.7 0.15 0.5 >2.1 1.3 VDDO - 0.85 Typical Maximum Units V V V V V
Output Low Voltage; NOTE 2 <0.9 VOL NOTE 1: VCMR, VPP defined for driving TEST_CLK input with differential levels other than SSTL_2. NOTE 2: Outputs terminated with 50 to ground.
TABLE 3F. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V10% OR 2.5V10%, VDDO = 2.5V10%, TA = -40C TO 85C
Symbol Parameter VOD VPP VCMR VOH Output Differential Voltage Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1 Output High Voltage; NOTE 2 Test Conditions Minimum 0.7 0.15 0.5 >1.77 1.3 VDDO - 0.85 Typical Maximum Units V V V V V
Output Low Voltage; NOTE 2 <0.73 VOL NOTE 1: VCMR, VPP defined for driving TEST_CLK input with differential levels other than SSTL_2. NOTE 2: Outputs terminated with 50 to ground.
TABLE 3G. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V10% OR 2.5V10%, VDDO = 1.8V5%, TA = -40C TO 85C
Symbol Parameter VOD VPP VCMR VOH Output Differential Voltage Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1 Output High Voltage; NOTE 2 Test Conditions Minimum 0.7 0.15 0.5 >1.19 1.3 VDDO - 0.85 Typical Maximum Units V V V V V
Output Low Voltage; NOTE 2 <0.615 VOL NOTE 1: VCMR, VPP defined for driving TEST_CLK input with differential levels other than SSTL_2. NOTE 2: Outputs terminated with 50 to ground.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
Test Conditions Minimum 23.33 Typical 26.5625 Maximum 28.33 50 7 1 Units MHz pF mW
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. Fundamental
TABLE 5. AC CHARACTERISTICS, TA = -40C TO 85C
Symbol Parameter Test Conditions F_SEL[1:0] = 00 fOUT Output Frequency F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 Minimum 186.67 140 93.33 46.67 TBD 212.5MHz, (637kHz - 10MHz) 159.375MHz, (637kHz - 10MHz) 0.80 0.78 0.50 0.81 0.79 650 Typical Maximum 226.66 170 113.33 56.66 Units MHz MHz MHz MHz ps ps ps ps ps ps ps %
tsk(o)
Output Skew; NOTE 1, 2
tjit(O)
RMS Phase Jitter (Random); NOTE 3
156.25MHz, (1.875MHz - 20MHz) 106.25MHz, (637kHz - 10MHz) 53.125MHz, (637kHz - 10MHz)
t R / tF
Output Rise/Fall Time
20% to 80%
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
+1.65V +/- 10% +1.65V +/- 10% Zo = 50 Ohm
+1.25V +/- 10%
SCOPE
+1.25V +/- 10% Zo = 50 Ohm
SCOPE
VDD
VDDO SSTL Driv er GND
50 Ohm
VDD
VDDO SSTL Driv er GND
50 Ohm
50 Ohm Zo = 50 Ohm -1.65V +/- 10%
50 Ohm Zo = 50 Ohm -1.25V +/- 10%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
nQx Qx nQy Qy
tsk(o)
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT SKEW
RMS PHASE JITTER
nQ0:nQ3 80% Clock Outputs 80% VSW I N G 20% tR tF
odc =
Q0:Q3
Pulse Width t
PERIOD
20%
t PW t PERIOD
OUTPUT RISE/FALL TIME
848004AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS848004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F V DDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS848004I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
ICS848004I
Figure 2. CRYSTAL INPUt INTERFACE
848004AGI
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
with the vendor of the driver component to confirm the driver termination requirements. The SSTL termination shown in these examples are also suitable for ICS48004I SSTL output drivers.
SSTL INTERFACE
Figures 3A to 3C show interface example of ICS848004I SOCKET/nSOCKET input driven by an SSTL driver. The input interfaces suggested here are examples only. Please consult
2.5V
1.25V 2.5V 2.5V R1 60 SSTL Zo = 60 Ohm SOCKET_CLK Zo = 60 Ohm nSOCKET_CLK
R1 120 R2 120 Zo = 60 Ohm nSOCKET_CLK 2.5V R3 120 R4 120 SOCKET_CLK SSTL Zo = 60 Ohm
R2 60
FIGURE 3A. TYPICAL SSTL INTERFACE BEING AVAILABLE
FOR
VDD/2 = 1.25V
FIGURE 3B. SSTL INTERFACE FOR VDD/2 = 1.25V WITH NO AVAILABLE
2.5V 2.5V SSTL R1 25 Zo = 60 Ohm R2 25 R3 120 nSOCKET_CLK Zo = 60 Ohm SOCKET_CLK
FIGURE 3C. DIFFERENTIAL SSTL INTERFACE
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REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS848004I is: 2951
848004AGI
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REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS848004I
FEMTOCLOCKSTMCRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER
Marking ICS848004AGI ICS848004AGI Package 24 Lead TSSOP 24 Lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS848004AGI ICS848004AGIT
The aforementioned trademarks, HiPerClockSTM and FEMTOCLOCKSTM are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 848004AGI
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